The present invention relates to a capacitance detection circuit that can be used with an acceleration sensor, and more specifically, to a capacitance detection circuit incorporating a voltage compensation circuit that compensates for deviations of a reference voltage.
An acceleration sensor includes a capacitance-voltage conversion circuit (hereinafter referred to as the “C-V circuit”) for converting capacitance fluctuation of a sensor element caused by changes in a physical quantity (acceleration) to an electrical signal. A sensor output is obtained by amplifying the electrical signal generated by the C-V circuit.
FIG. 1 is a schematic circuit diagram of a conventional capacitance detection circuit. The capacitance detection circuit includes a C-V circuit 100 that is connected to a sensor element 10. The C-V circuit 100 further includes an operational amplifier 20, switch element 22, and feedback capacitor 24. The operational amplifier 20 has an inversion input terminal that is connected to the sensor element 10, a non-inversion input terminal that receives a reference voltage Vr, and an output terminal that outputs a detection signal Vo. The switch element 22 is connected between the inversion input terminal and the output terminal of the operational amplifier 20. The feedback capacitor 24 is connected in parallel to the switch element 22. The switch element 22 is activated and deactivated by a control signal provided from a drive circuit (not shown). Specifically, the control signal activates the switch element 22 in a reset phase, and deactivates the switch element 22 in a sampling phase.
The sensor element 10 includes first and second variable capacitors 12 and 14 and a parasitic capacitor element 16. The first variable capacitor 12 has a movable electrode 12a, which is connected to the inversion input terminal of the operational amplifier 20, and a fixed electrode 12b, which receives a carrier wave Va that functions as a drive signal. The second variable capacitor 14 has a movable electrode 14a, which is connected to the movable electrode 12a of the first variable capacitor 12, and a fixed electrode 14b, which receives a carrier wave Vb that functions as a drive signal. The carrier waves Va and Vb have opposite phases and are cyclically applied to the fixed electrodes 12b and 14b by the drive circuit. In the reset phase, for example, the carrier wave Va is set to voltage V1 (for example, 0 V), and the carrier wave Vb is set to voltage V2 (for example, 3 V), which has a phase opposite to the voltage V1. In the sampling phase, the carrier wave Va is set to the voltage V2, and the carrier wave Vb is set to the voltage V1. The parasitic capacitor element 16 is a parasitic capacitor configured within the sensor element 10. In FIG. 1, the parasitic capacitor element 16 is represented as a parasitic capacitor 16 including a first electrode, which is connected to the inversion input terminal of the operational amplifier 20, and a second electrode, which receives a reference voltage Vr.
The movable electrodes 12a and 14a of the first and second variable capacitors 12 and 14 are moved by the same amount in the same direction (the fixed electrode 12b side or fixed electrode 14b side) in accordance with changes in acceleration added to the sensor element 10. The movement of the movable electrodes 12a and 14a produce changes in the differential capacitor formed by the variable capacitors 12 and 14. Thus, the sensor element 10 detects a change in the acceleration as a change in the capacitance of the variable capacitors 12 and 14.
The operation of the C-V circuit 100 will now be described.
During the reset phase, the switch element 22 is activated, voltage V1 (Va) is applied to the fixed electrode 12b of the first variable capacitor 12, and voltage V2 (Vb) is applied to the fixed electrode 14b of the second variable capacitor 14. As a result, the feedback capacitor 24 is discharged. In this state, the operational amplifier 20 outputs a detection signal Vo, which has substantially the same level as the reference voltage Vr.
The sampling phase then starts. During the sampling phase, the switch element 22 is deactivated, voltage V2 (Va) is applied to the fixed electrode 12b of the first variable capacitor 12, and voltage V1 (Vb) is applied to the fixed electrode 14b of the second variable capacitor 14. As a result, the feedback capacitor 24 is charged in correspondence with the displacement of the movable electrodes 12a and 14a. Accordingly, the operational amplifier 20 generates a detection signal Vo corresponding to the charging of the feedback capacitor 24, or change in the capacitance of the sensor element 10. Then, the reset phase and sampling phases are alternately repeated by the operation described above.
In such an acceleration detection operation, a deviation occurs in the output of the operational amplifier 20 when the reference voltage Vr of the operational amplifier 20 fluctuates between the reset phase and sampling phase due to the effect of noise or the unstable operation of a regulator (not shown in the drawing) that generates the reference voltage Vr. When the reference voltage Vr fluctuates by a deviation amount Vd during the sampling phase, a reference voltage that includes the deviation amount Vd (that is, Vr+Vd) is supplied to the non-inverting input terminal of the operational amplifier 20. In this case, the inverting input terminal of the operational amplifier 20 is biased to the same potential as the reference voltage (Vr+Vd) by the negative feedback function (imaginary short-circuiting) of the operational amplifier 20. That is, the voltage fed back to the inverting input terminal of the operational amplifier 20 is shifted by the same amount as the deviation amount Vd of the reference voltage Vt. In this state, the output deviation amount Vc of the operational amplifier 20 caused by the deviation amount Vd may be expressed by the equation shown below.Vc=[(Cg1+Cg2+CF)/CF]Vd  Equation 1
In equation 1, [Cg1] represents the capacitance of the first variable capacitor 12, [Cg2] represents the capacitance of the second variable capacitor 14, and [CF] represents the capacitance of the feedback capacitor 24.
Equation 1 above signifies that the deviation amount Vd of the reference voltage Vr between the reset and sampling phases is amplified by the gain G1 ((Cg1+Cg2+CF)/CF) of the entire system including the sensor element 10 and C-V circuit 100, and the amplified deviation is reflected in the output voltage of the operational amplifier 20. That is, the output voltage of the operational amplifier 20 is represented as a value (V0+Vc), which includes the output deviation amount Vc of a multiple of the gain G1 of the deviation amount Vd relative to a normal detection value Vo.
Japanese Laid-Open Patent Publication No. 2006-284272 discloses a noise reduction scheme applicable to a C-V circuit for an acceleration sensor. The acceleration sensor described in this publication (refer to FIG. 1 of the publication) includes a sensor element 10, a drive circuit 30 for generating carrier waves PW1 and PW2 that drive the sensor element 10, a C-V circuit 21 for detecting a capacitance fluctuation value of the sensor 10 based on a reference voltage Vref, and a filter circuit 40 arranged between a power source 50 and the drive circuit 30. In this acceleration sensor, the operating voltage of the drive circuit 30 is supplied from the power source 50 via the filter circuit 40. The filter circuit 40 eliminates the noise included in the gain of the supplied power between the power source 50 and the drive circuit 30. Therefore, the voltages of the carrier waves PW1 and PW2 supplied from the drive circuit 30 to the sensor element 10 are prevented from being fluctuated by noise.
However, the conventional circuit described in the publication does not take into consideration the possibility of fluctuation of the reference voltage Vref of the C-V circuit 21. As described above, there is a possibility that the reference voltage Vref of the C-V circuit 21 may fluctuate due to the influence of noise and the unstable operation of the regulator. Fluctuation of the reference voltage Vref may produce an output deviation amount in the C-V circuit 21 that is larger than the deviation amount of the reference voltage Vref. This lowers the output accuracy (detection accuracy) of the C-V circuit 21. Accordingly, the conventional circuit described in the above publications has problems similar to those of the conventional circuit of FIG. 1.
A high performance regulator capable of generating a reference voltage with high precision may be designed to prevent such a deviation in the reference voltage. However, this would increase the chip area, raise the production cost, and thus may not be able to satisfy system requirements. A practical circuit that compensates for the deviation of the reference voltage with a simple and inexpensive configuration is thus desired.